这似乎是 spacedesk 的一个问题，安装后 WSL2 不再启动，并抛出错误“请启用虚拟机平台 Windows 功能并确保在 BIOS 中启用了虚拟化。有关信息，请访问https://aka.ms/wsl2-install”。
spacedesk 论坛上对该问题进行了讨论，但没有解决方案。 https://www.spacedesk.net/forums/topic/wsl2-not-starting-after-spacedesk-installation/
- 安装之前 WSL2 运行良好。
- UEFI 已启用虚拟化。
- Windows 功能中启用了虚拟机平台和适用于 Linux 的 Windows 子系统。
- 尝试关闭这些功能并打开却没有任何效果。
- 卸载 spacedesk 并不能解决问题。
有人可以帮忙找到解决方案吗？
CoreInfo64 转储
AMD FX(tm)-8350 Eight-Core Processor
AMD64 Family 21 Model 2 Stepping 0, AuthenticAMD
Microcode signature: 00000000
HTT * Multicore
CET - Supports Control Flow Enforcement Technology
Kernel CET - Kernel-mode CET Enabled
User CET - User-mode CET Allowed
HYPERVISOR - Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM * Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT * Supports AMD SKINIT
SGX - Supports Intel SGX
NX * Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB * Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS - Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT * Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a * Supports Streaming SIMDR Extensions 4a
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES * Supports AES extensions
AVX * Supports AVX instruction extensions
AVX2 - Supports AVX2 instruction extensions
AVX-512-F - Supports AVX-512 Foundation instructions
AVX-512-DQ - Supports AVX-512 double and quadword instructions
AVX-512-IFAMA - Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF - Supports AVX-512 prefetch instructions
AVX-512-ER - Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD - Supports AVX-512 conflict detection instructions
AVX-512-BW - Supports AVX-512 byte and word instructions
AVX-512-VL - Supports AVX-512 vector length instructions
FMA * Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 * Supports bit manipulation extensions 1
BMI2 - Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C * Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR * Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLMULDQ * Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
LZCNT * Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 - Can write history of 64-bit branch addresses
DS - Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM - Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR - Supports disabling task priority messages
EIST - Supports Enhanced Intel Speedstep
ACPI - Implements MSR for power management
TM - Implements thermal monitor circuitry
TM2 - Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE - Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 0000000D (Basic), 8000001E (Extended).
Maximum implemented address width: 48 bits (virtual), 48 bits (physical).
Processor signature: 00600F20
Logical to Physical Processor Map:
**------ Physical Processor 0 (Hyperthreaded)
--**---- Physical Processor 1 (Hyperthreaded)
----**-- Physical Processor 2 (Hyperthreaded)
------** Physical Processor 3 (Hyperthreaded)
Logical Processor to Socket Map:
******** Socket 0
Logical Processor to NUMA Node Map:
******** NUMA Node 0
No NUMA nodes.
Logical Processor to Cache Map:
*------- Data Cache 0, Level 1, 16 KB, Assoc 4, LineSize 64
**------ Instruction Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64
**------ Unified Cache 0, Level 2, 2 MB, Assoc 16, LineSize 64
******** Unified Cache 1, Level 3, 8 MB, Assoc 64, LineSize 64
-*------ Data Cache 1, Level 1, 16 KB, Assoc 4, LineSize 64
--*----- Data Cache 2, Level 1, 16 KB, Assoc 4, LineSize 64
--**---- Instruction Cache 1, Level 1, 64 KB, Assoc 2, LineSize 64
--**---- Unified Cache 2, Level 2, 2 MB, Assoc 16, LineSize 64
---*---- Data Cache 3, Level 1, 16 KB, Assoc 4, LineSize 64
----*--- Data Cache 4, Level 1, 16 KB, Assoc 4, LineSize 64
----**-- Instruction Cache 2, Level 1, 64 KB, Assoc 2, LineSize 64
----**-- Unified Cache 3, Level 2, 2 MB, Assoc 16, LineSize 64
-----*-- Data Cache 5, Level 1, 16 KB, Assoc 4, LineSize 64
------*- Data Cache 6, Level 1, 16 KB, Assoc 4, LineSize 64
------** Instruction Cache 3, Level 1, 64 KB, Assoc 2, LineSize 64
------** Unified Cache 4, Level 2, 2 MB, Assoc 16, LineSize 64
-------* Data Cache 7, Level 1, 16 KB, Assoc 4, LineSize 64
Logical Processor to Group Map:
******** Group 0
答案1
您可能想要尝试的一件事是名为“限制 CPUID 最大值”或类似名称的 BIOS 选项。Microsoft 的虚拟机管理程序对此设置存在问题（并且没有报告）。切换它会禁用我系统上的 WSL2 和 Hyper-V，即使所有其他虚拟化功能（包括 WSL1）都可以正常工作。