dtb phandle 添加到 IOMMU 失败

dtb phandle 添加到 IOMMU 失败

我有这个错误:

(XEN) *** LOADING DOMAIN 0 ***
(XEN) Loading d0 kernel from boot module @ 0000000018000000
(XEN) Allocating 1:1 mappings totalling 1024MB for dom0:
(XEN) BANK[0] 0x00000020000000-0x00000060000000 (1024MB)
(XEN) Grant table range: 0x00000000200000-0x00000000240000
(XEN) Failed to add /axi/dma-controller@fd500000 to the IOMMU
(XEN) Device tree generation failed (-22).
(XEN) 
(XEN) ****************************************
(XEN) Panic on CPU 0:
(XEN) Could not set up DOM0 guest OS
(XEN) ****************************************

xen/drivers/passthrough/device_tree.cxen 中正在寻找 phandle 在我的dma-controller@fd500000? Phandle 似乎是由 dtc 自动生成的,但我不明白它是如何工作的。我尝试添加#stream-id-cells = <1>;但没有成功。

 /*
 * According to the Documentation/devicetree/bindings/iommu/iommu.txt
 * from Linux.
 */
while ( !dt_parse_phandle_with_args(np, "iommus", "#iommu-cells",
                                    index, &iommu_spec) )
{

我的 dtb 文件:

#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>

/ {
    compatible = "xlnx,zynqmp";
    #address-cells = <2>;
    #size-cells = <2>;

    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu0: cpu@0 {
            compatible = "arm,cortex-a53";
            device_type = "cpu";
            enable-method = "psci";
            operating-points-v2 = <&cpu_opp_table>;
            reg = <0x0>;
            cpu-idle-states = <&CPU_SLEEP_0>;
            next-level-cache = <&L2>;
        };

        cpu1: cpu@1 {
            compatible = "arm,cortex-a53";
            device_type = "cpu";
            enable-method = "psci";
            reg = <0x1>;
            operating-points-v2 = <&cpu_opp_table>;
            cpu-idle-states = <&CPU_SLEEP_0>;
            next-level-cache = <&L2>;
        };

        cpu2: cpu@2 {
            compatible = "arm,cortex-a53";
            device_type = "cpu";
            enable-method = "psci";
            reg = <0x2>;
            operating-points-v2 = <&cpu_opp_table>;
            cpu-idle-states = <&CPU_SLEEP_0>;
            next-level-cache = <&L2>;
        };

        cpu3: cpu@3 {
            compatible = "arm,cortex-a53";
            device_type = "cpu";
            enable-method = "psci";
            reg = <0x3>;
            operating-points-v2 = <&cpu_opp_table>;
            cpu-idle-states = <&CPU_SLEEP_0>;
            next-level-cache = <&L2>;
        };

        L2: l2-cache {
            compatible = "cache";
            cache-level = <2>;
        };

        idle-states {
            entry-method = "psci";

            CPU_SLEEP_0: cpu-sleep-0 {
                compatible = "arm,idle-state";
                arm,psci-suspend-param = <0x40000000>;
                local-timer-stop;
                entry-latency-us = <300>;
                exit-latency-us = <600>;
                min-residency-us = <10000>;
            };
        };
    };

    cpu_opp_table: opp-table-cpu {
        compatible = "operating-points-v2";
        opp-shared;
        opp00 {
            opp-hz = /bits/ 64 <1199999988>;
            opp-microvolt = <1000000>;
            clock-latency-ns = <500000>;
        };
        opp01 {
            opp-hz = /bits/ 64 <599999994>;
            opp-microvolt = <1000000>;
            clock-latency-ns = <500000>;
        };
        opp02 {
            opp-hz = /bits/ 64 <399999996>;
            opp-microvolt = <1000000>;
            clock-latency-ns = <500000>;
        };
        opp03 {
            opp-hz = /bits/ 64 <299999997>;
            opp-microvolt = <1000000>;
            clock-latency-ns = <500000>;
        };
    };

    zynqmp_ipi: zynqmp_ipi {
        u-boot,dm-pre-reloc;
        compatible = "xlnx,zynqmp-ipi-mailbox";
        interrupt-parent = <&gic>;
        interrupts = <0 35 4>;
        xlnx,ipi-id = <0>;
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;

        ipi_mailbox_pmu1: mailbox@ff9905c0 {
            u-boot,dm-pre-reloc;
            reg = <0x0 0xff9905c0 0x0 0x20>,
                  <0x0 0xff9905e0 0x0 0x20>,
                  <0x0 0xff990e80 0x0 0x20>,
                  <0x0 0xff990ea0 0x0 0x20>;
            reg-names = "local_request_region",
                    "local_response_region",
                    "remote_request_region",
                    "remote_response_region";
            #mbox-cells = <1>;
            xlnx,ipi-id = <4>;
        };
    };

    dcc: dcc {
        compatible = "arm,dcc";
        status = "disabled";
        u-boot,dm-pre-reloc;
    };

    pmu {
        compatible = "arm,armv8-pmuv3";
        interrupt-parent = <&gic>;
        interrupts = <0 143 4>,
                 <0 144 4>,
                 <0 145 4>,
                 <0 146 4>;
        interrupt-affinity = <&cpu0>,
                     <&cpu1>;
    };

    psci {
        compatible = "arm,psci-0.2";
        method = "smc";
    };

    firmware {
        zynqmp_firmware: zynqmp-firmware {
            compatible = "xlnx,zynqmp-firmware";
            #power-domain-cells = <1>;
            method = "smc";
            u-boot,dm-pre-reloc;

            zynqmp_power: zynqmp-power {
                u-boot,dm-pre-reloc;
                compatible = "xlnx,zynqmp-power";
                interrupt-parent = <&gic>;
                interrupts = <0 35 4>;
                mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
                mbox-names = "tx", "rx";
            };

            nvmem_firmware {
                compatible = "xlnx,zynqmp-nvmem-fw";
                #address-cells = <1>;
                #size-cells = <1>;

                soc_revision: soc_revision@0 {
                    reg = <0x0 0x4>;
                };
                /* efuse access */
                efuse_dna: efuse_dna@c {
                    reg = <0xc 0xc>;
                };
                efuse_usr0: efuse_usr0@20 {
                    reg = <0x20 0x4>;
                };
                efuse_usr1: efuse_usr1@24 {
                    reg = <0x24 0x4>;
                };
                efuse_usr2: efuse_usr2@28 {
                    reg = <0x28 0x4>;
                };
                efuse_usr3: efuse_usr3@2c {
                    reg = <0x2c 0x4>;
                };
                efuse_usr4: efuse_usr4@30 {
                    reg = <0x30 0x4>;
                };
                efuse_usr5: efuse_usr5@34 {
                    reg = <0x34 0x4>;
                };
                efuse_usr6: efuse_usr6@38 {
                    reg = <0x38 0x4>;
                };
                efuse_usr7: efuse_usr7@3c {
                    reg = <0x3c 0x4>;
                };
                efuse_miscusr: efuse_miscusr@40 {
                    reg = <0x40 0x4>;
                };
                efuse_chash: efuse_chash@50 {
                    reg = <0x50 0x4>;
                };
                efuse_pufmisc: efuse_pufmisc@54 {
                    reg = <0x54 0x4>;
                };
                efuse_sec: efuse_sec@58 {
                    reg = <0x58 0x4>;
                };
                efuse_spkid: efuse_spkid@5c {
                    reg = <0x5c 0x4>;
                };
                efuse_ppk0hash: efuse_ppk0hash@a0 {
                    reg = <0xa0 0x30>;
                };
                efuse_ppk1hash: efuse_ppk1hash@d0 {
                    reg = <0xd0 0x30>;
                };
            };

            zynqmp_pcap: pcap {
                compatible = "xlnx,zynqmp-pcap-fpga";
                clock-names = "ref_clk";
            };

            zynqmp_reset: reset-controller {
                compatible = "xlnx,zynqmp-reset";
                #reset-cells = <1>;
            };

            pinctrl0: pinctrl {
                compatible = "xlnx,zynqmp-pinctrl";
                status = "disabled";
            };

            modepin_gpio: gpio {
                compatible = "xlnx,zynqmp-gpio-modepin";
                gpio-controller;
                #gpio-cells = <2>;
            };
        };
    };

    timer {
        compatible = "arm,armv8-timer";
        interrupt-parent = <&gic>;
        interrupts = <1 13 0xf08>,
                 <1 14 0xf08>,
                 <1 11 0xf08>,
                 <1 10 0xf08>;
    };

    edac {
        compatible = "arm,cortex-a53-edac";
    };

    fpga_full: fpga-full {
        compatible = "fpga-region";
        fpga-mgr = <&zynqmp_pcap>;
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;
    };

    amba: axi {
        compatible = "simple-bus";
        u-boot,dm-pre-reloc;
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;

        can0: can@ff060000 {
            compatible = "xlnx,zynq-can-1.0";
            status = "disabled";
            clock-names = "can_clk", "pclk";
            reg = <0x0 0xff060000 0x0 0x1000>;
            interrupts = <0 23 4>;
            interrupt-parent = <&gic>;
            tx-fifo-depth = <0x40>;
            rx-fifo-depth = <0x40>;
            power-domains = <&zynqmp_firmware PD_CAN_0>;
        };

        can1: can@ff070000 {
            compatible = "xlnx,zynq-can-1.0";
            status = "disabled";
            clock-names = "can_clk", "pclk";
            reg = <0x0 0xff070000 0x0 0x1000>;
            interrupts = <0 24 4>;
            interrupt-parent = <&gic>;
            tx-fifo-depth = <0x40>;
            rx-fifo-depth = <0x40>;
            power-domains = <&zynqmp_firmware PD_CAN_1>;
        };

        cci: cci@fd6e0000 {
            compatible = "arm,cci-400";
            status = "disabled";
            reg = <0x0 0xfd6e0000 0x0 0x9000>;
            ranges = <0x0 0x0 0xfd6e0000 0x10000>;
            #address-cells = <1>;
            #size-cells = <1>;

            pmu@9000 {
                compatible = "arm,cci-400-pmu,r1";
                reg = <0x9000 0x5000>;
                interrupt-parent = <&gic>;
                interrupts = <0 123 4>,
                         <0 123 4>,
                         <0 123 4>,
                         <0 123 4>,
                         <0 123 4>;
            };
        };

        /* GDMA */
        fpd_dma_chan1: dma-controller@fd500000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xfd500000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 124 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            #stream-id-cells = <0x01>;
            xlnx,bus-width = <128>;
            iommus = <&smmu 0x14e8>;
            power-domains = <&zynqmp_firmware PD_GDMA>;
        };

        fpd_dma_chan2: dma-controller@fd510000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xfd510000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 125 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            #stream-id-cells = <1>;
            xlnx,bus-width = <128>;
            iommus = <&smmu 0x14e9>;
            power-domains = <&zynqmp_firmware PD_GDMA>;
        };

        fpd_dma_chan3: dma-controller@fd520000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xfd520000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 126 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            #stream-id-cells = <1>;
            xlnx,bus-width = <128>;
            iommus = <&smmu 0x14ea>;
            power-domains = <&zynqmp_firmware PD_GDMA>;
        };

        fpd_dma_chan4: dma-controller@fd530000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xfd530000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 127 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            #stream-id-cells = <1>;
            xlnx,bus-width = <128>;
            iommus = <&smmu 0x14eb>;
            power-domains = <&zynqmp_firmware PD_GDMA>;
        };

        fpd_dma_chan5: dma-controller@fd540000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xfd540000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 128 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            #stream-id-cells = <1>;
            xlnx,bus-width = <128>;
            iommus = <&smmu 0x14ec>;
            power-domains = <&zynqmp_firmware PD_GDMA>;
        };

        fpd_dma_chan6: dma-controller@fd550000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xfd550000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 129 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            #stream-id-cells = <1>;
            xlnx,bus-width = <128>;
            iommus = <&smmu 0x14ed>;
            power-domains = <&zynqmp_firmware PD_GDMA>;
        };

        fpd_dma_chan7: dma-controller@fd560000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xfd560000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 130 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
             #stream-id-cells = <1>;
            xlnx,bus-width = <128>;
            iommus = <&smmu 0x14ee>;
            power-domains = <&zynqmp_firmware PD_GDMA>;
        };

        fpd_dma_chan8: dma-controller@fd570000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xfd570000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 131 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            #stream-id-cells = <1>;
            xlnx,bus-width = <128>;
            iommus = <&smmu 0x14ef>;
            power-domains = <&zynqmp_firmware PD_GDMA>;
        };

        gic: interrupt-controller@f9010000 {
            compatible = "arm,gic-400";
            #interrupt-cells = <3>;
            reg = <0x0 0xf9010000 0x0 0x10000>,
                  <0x0 0xf9020000 0x0 0x20000>,
                  <0x0 0xf9040000 0x0 0x20000>,
                  <0x0 0xf9060000 0x0 0x20000>;
            interrupt-controller;
            interrupt-parent = <&gic>;
            interrupts = <1 9 0xf04>;
        };

        gpu: gpu@fd4b0000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-mali", "arm,mali-400";
            reg = <0x0 0xfd4b0000 0x0 0x10000>;
            interrupt-parent = <&gic>;
            interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
            interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
            clock-names = "bus", "core";
            power-domains = <&zynqmp_firmware PD_GPU>;
        };

        /* LPDDMA default allows only secured access. inorder to enable
         * These dma channels, Users should ensure that these dma
         * Channels are allowed for non secure access.
         */
        lpd_dma_chan1: dma-controller@ffa80000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xffa80000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 77 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            xlnx,bus-width = <64>;
            /* iommus = <&smmu 0x868>; */
            power-domains = <&zynqmp_firmware PD_ADMA>;
        };

        lpd_dma_chan2: dma-controller@ffa90000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xffa90000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 78 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            xlnx,bus-width = <64>;
            /* iommus = <&smmu 0x869>; */
            power-domains = <&zynqmp_firmware PD_ADMA>;
        };

        lpd_dma_chan3: dma-controller@ffaa0000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xffaa0000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 79 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            xlnx,bus-width = <64>;
            /* iommus = <&smmu 0x86a>; */
            power-domains = <&zynqmp_firmware PD_ADMA>;
        };

        lpd_dma_chan4: dma-controller@ffab0000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xffab0000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 80 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            xlnx,bus-width = <64>;
            /* iommus = <&smmu 0x86b>; */
            power-domains = <&zynqmp_firmware PD_ADMA>;
        };

        lpd_dma_chan5: dma-controller@ffac0000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xffac0000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 81 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            xlnx,bus-width = <64>;
            /* iommus = <&smmu 0x86c>; */
            power-domains = <&zynqmp_firmware PD_ADMA>;
        };

        lpd_dma_chan6: dma-controller@ffad0000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xffad0000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 82 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            xlnx,bus-width = <64>;
            /* iommus = <&smmu 0x86d>; */
            power-domains = <&zynqmp_firmware PD_ADMA>;
        };

        lpd_dma_chan7: dma-controller@ffae0000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xffae0000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 83 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            xlnx,bus-width = <64>;
            /* iommus = <&smmu 0x86e>; */
            power-domains = <&zynqmp_firmware PD_ADMA>;
        };

        lpd_dma_chan8: dma-controller@ffaf0000 {
            status = "disabled";
            compatible = "xlnx,zynqmp-dma-1.0";
            reg = <0x0 0xffaf0000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 84 4>;
            clock-names = "clk_main", "clk_apb";
            #dma-cells = <1>;
            xlnx,bus-width = <64>;
            /* iommus = <&smmu 0x86f>; */
            power-domains = <&zynqmp_firmware PD_ADMA>;
        };

        mc: memory-controller@fd070000 {
            compatible = "xlnx,zynqmp-ddrc-2.40a";
            reg = <0x0 0xfd070000 0x0 0x30000>;
            interrupt-parent = <&gic>;
            interrupts = <0 112 4>;
        };

        nand0: nand-controller@ff100000 {
            compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
            status = "disabled";
            reg = <0x0 0xff100000 0x0 0x1000>;
            clock-names = "controller", "bus";
            interrupt-parent = <&gic>;
            interrupts = <0 14 4>;
            #address-cells = <1>;
            #size-cells = <0>;
            iommus = <&smmu 0x872>;
            power-domains = <&zynqmp_firmware PD_NAND>;
        };

        gem0: ethernet@ff0b0000 {
            compatible = "xlnx,zynqmp-gem", "cdns,gem";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 57 4>, <0 57 4>;
            reg = <0x0 0xff0b0000 0x0 0x1000>;
            clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
            #address-cells = <1>;
            #size-cells = <0>;
            iommus = <&smmu 0x874>;
            power-domains = <&zynqmp_firmware PD_ETH_0>;
            resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
            reset-names = "gem0_rst";
        };

        gem1: ethernet@ff0c0000 {
            compatible = "xlnx,zynqmp-gem", "cdns,gem";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 59 4>, <0 59 4>;
            reg = <0x0 0xff0c0000 0x0 0x1000>;
            clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
            #address-cells = <1>;
            #size-cells = <0>;
            iommus = <&smmu 0x875>;
            power-domains = <&zynqmp_firmware PD_ETH_1>;
            resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
            reset-names = "gem1_rst";
        };

        gem2: ethernet@ff0d0000 {
            compatible = "xlnx,zynqmp-gem", "cdns,gem";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 61 4>, <0 61 4>;
            reg = <0x0 0xff0d0000 0x0 0x1000>;
            clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
            #address-cells = <1>;
            #size-cells = <0>;
            iommus = <&smmu 0x876>;
            power-domains = <&zynqmp_firmware PD_ETH_2>;
            resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
            reset-names = "gem2_rst";
        };

        gem3: ethernet@ff0e0000 {
            compatible = "xlnx,zynqmp-gem", "cdns,gem";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 63 4>, <0 63 4>;
            reg = <0x0 0xff0e0000 0x0 0x1000>;
            clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
            #address-cells = <1>;
            #size-cells = <0>;
            iommus = <&smmu 0x877>;
            power-domains = <&zynqmp_firmware PD_ETH_3>;
            resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
            reset-names = "gem3_rst";
        };

        gpio: gpio@ff0a0000 {
            compatible = "xlnx,zynqmp-gpio-1.0";
            status = "disabled";
            #gpio-cells = <0x2>;
            gpio-controller;
            interrupt-parent = <&gic>;
            interrupts = <0 16 4>;
            interrupt-controller;
            #interrupt-cells = <2>;
            reg = <0x0 0xff0a0000 0x0 0x1000>;
            power-domains = <&zynqmp_firmware PD_GPIO>;
        };

        i2c0: i2c@ff020000 {
            compatible = "cdns,i2c-r1p14";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 17 4>;
            reg = <0x0 0xff020000 0x0 0x1000>;
            #address-cells = <1>;
            #size-cells = <0>;
            power-domains = <&zynqmp_firmware PD_I2C_0>;
        };

        i2c1: i2c@ff030000 {
            compatible = "cdns,i2c-r1p14";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 18 4>;
            reg = <0x0 0xff030000 0x0 0x1000>;
            #address-cells = <1>;
            #size-cells = <0>;
            power-domains = <&zynqmp_firmware PD_I2C_1>;
        };

        ocm: memory-controller@ff960000 {
            compatible = "xlnx,zynqmp-ocmc-1.0";
            reg = <0x0 0xff960000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <0 10 4>;
        };

        qspi: spi@ff0f0000 {
            u-boot,dm-pre-reloc;
            compatible = "xlnx,zynqmp-qspi-1.0";
            status = "disabled";
            clock-names = "ref_clk", "pclk";
            interrupts = <0 15 4>;
            interrupt-parent = <&gic>;
            num-cs = <1>;
            reg = <0x0 0xff0f0000 0x0 0x1000>,
                  <0x0 0xc0000000 0x0 0x8000000>;
            #address-cells = <1>;
            #size-cells = <0>;
            iommus = <&smmu 0x873>;
            power-domains = <&zynqmp_firmware PD_QSPI>;
        };

        psgtr: phy@fd400000 {
            compatible = "xlnx,zynqmp-psgtr-v1.1";
            status = "disabled";
            reg = <0x0 0xfd400000 0x0 0x40000>,
                  <0x0 0xfd3d0000 0x0 0x1000>;
            reg-names = "serdes", "siou";
            #phy-cells = <4>;
        };

        rtc: rtc@ffa60000 {
            compatible = "xlnx,zynqmp-rtc";
            status = "disabled";
            reg = <0x0 0xffa60000 0x0 0x100>;
            interrupt-parent = <&gic>;
            interrupts = <0 26 4>, <0 27 4>;
            interrupt-names = "alarm", "sec";
            calibration = <0x7FFF>;
        };

        sata: ahci@fd0c0000 {
            compatible = "ceva,ahci-1v84";
            status = "disabled";
            reg = <0x0 0xfd0c0000 0x0 0x2000>;
            interrupt-parent = <&gic>;
            interrupts = <0 133 4>;
            power-domains = <&zynqmp_firmware PD_SATA>;
            resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
            /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, */
            /*   <&smmu 0x4c2>, <&smmu 0x4c3>; */
            /* dma-coherent; */
        };

        sdhci0: mmc@ff160000 {
            u-boot,dm-pre-reloc;
            compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 48 4>;
            reg = <0x0 0xff160000 0x0 0x1000>;
            clock-names = "clk_xin", "clk_ahb";
            iommus = <&smmu 0x870>;
            #clock-cells = <1>;
            clock-output-names = "clk_out_sd0", "clk_in_sd0";
            power-domains = <&zynqmp_firmware PD_SD_0>;
            resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
        };

        sdhci1: mmc@ff170000 {
            u-boot,dm-pre-reloc;
            compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 49 4>;
            reg = <0x0 0xff170000 0x0 0x1000>;
            clock-names = "clk_xin", "clk_ahb";
            iommus = <&smmu 0x871>;
            #clock-cells = <1>;
            clock-output-names = "clk_out_sd1", "clk_in_sd1";
            power-domains = <&zynqmp_firmware PD_SD_1>;
            resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
        };

        smmu: iommu@fd800000 {
            compatible = "arm,mmu-500";
            reg = <0x0 0xfd800000 0x0 0x20000>;
            #iommu-cells = <1>;
            status = "okay";
            #global-interrupts = <1>;
            interrupt-parent = <&gic>;
            interrupts = <0 155 4>,
                <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
                <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
                <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
                <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
        };

    

        watchdog0: watchdog@fd4d0000 {
            compatible = "cdns,wdt-r1p2";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 113 1>;
            reg = <0x0 0xfd4d0000 0x0 0x1000>;
            timeout-sec = <60>;
            reset-on-timeout;
        };

        lpd_watchdog: watchdog@ff150000 {
            compatible = "cdns,wdt-r1p2";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 52 1>;
            reg = <0x0 0xff150000 0x0 0x1000>;
            timeout-sec = <10>;
        };

        xilinx_ams: ams@ffa50000 {
            compatible = "xlnx,zynqmp-ams";
            status = "disabled";
            interrupt-parent = <&gic>;
            interrupts = <0 56 4>;
            interrupt-names = "ams-irq";
            reg = <0x0 0xffa50000 0x0 0x800>;
            reg-names = "ams-base";
            #address-cells = <1>;
            #size-cells = <1>;
            #io-channel-cells = <1>;
            ranges = <0 0 0xffa50800 0x800>;

            ams_ps: ams_ps@0 {
                compatible = "xlnx,zynqmp-ams-ps";
                status = "disabled";
                reg = <0x0 0x400>;
            };

            ams_pl: ams_pl@400 {
                compatible = "xlnx,zynqmp-ams-pl";
                status = "disabled";
                reg = <0x400 0x400>;
            };
        };

        zynqmp_dpdma: dma-controller@fd4c0000 {
            compatible = "xlnx,zynqmp-dpdma";
            status = "disabled";
            reg = <0x0 0xfd4c0000 0x0 0x1000>;
            interrupts = <0 122 4>;
            interrupt-parent = <&gic>;
            clock-names = "axi_clk";
            power-domains = <&zynqmp_firmware PD_DP>;
            dma-channels = <6>;
            iommus = <&smmu 0xce4>;
            #dma-cells = <1>;
        };

        zynqmp_dpaud_setting: dp_aud@fd4ac000 {
            compatible = "xlnx,zynqmp-dpaud-setting", "syscon";
            reg = <0x0 0xfd4ac000 0x0 0x1000>;
        };
    };
};

和 :

/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include "pl.dtsi"
#include "pcw.dtsi"
/ {
    chosen {
        bootargs = "earlycon clk_ignore_unused";
        stdout-path = "serial0:115200n8";
                
                #address-cells = <0x02>;
                #size-cells = <0x01>;

                xen,xen-bootargs = "console=dtuart dtuart=serial0 dom0_mem=1G bootscrub=0 maxcpus=1 timer_slop=0";
                xen,dom0-bootargs = "console=hvc0 earlycon=xen maxcpus=1 earlyprintk=xen clk_ignore_unused root=/dev/mmcblk0p2 rootwait quiet";
                
                dom0 {
                    compatible = "xen,linux-zimage", "xen,multiboot-module";
                    reg = <0x0 0x00080000 0x3100000>;
                };
    };
    aliases {
        ethernet0 = &gem2;
        i2c0 = &i2c0;
        i2c1 = &i2c1;
        serial0 = &uart0;
        serial1 = &uart1;
        spi0 = &qspi;
        spi1 = &spi0;
        spi2 = &spi1;
    };
    memory {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x7ff00000>;
    };
    cpus {
        /delete-node/ cpu@2 ;
        /delete-node/ cpu@3 ;
    };
};

&sdhci0 {
    non-removable;
    disable-wp;
    status = "okay";
};

&sdhci1 {
    status = "disabled";
};

&smmu {
    status = "okay";
};

&xilinx_ams {
    status = "okay";
};

&ams_ps {
    status = "okay";
};

&ams_pl {
    status = "okay";
};

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