我正在编写一个文档，其中必须在附录部分添加代码。我正在使用类，IEEEtran但在使用包添加代码时它对我没有任何帮助minted。有没有办法我可以使用完整页面编写完整的文本，并在必要时允许它制作分页？
这是一个有效的例子：
\documentclass{IEEEtran}
\usepackage{lipsum}
\usepackage[]{minted}
\begin{document}
\section{Introduction}
\lipsum
\section{Material}
\lipsum
\appendices
\section{BaudRate}
\begin{minted}[breaklines,linenos=true,numberblanklines=true]{vhdl}
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRate is
port(
RST :in std_logic;
CLK :in std_logic;
NBaud :in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud :out std_logic -- Base frecuency
);
end BaudRate;
architecture simple of BaudRate is
signal Qp,Qn,NB : std_logic_vector(18 downto 0);
begin
COMB: process(NBaud,Qp)
begin
case NBaud is
when "0000"=>
NB<= "1101110111110010001"; -- 110 Bauds
when "0001"=>
NB<= "0101000101100001010"; -- 300 Bauds
when "0010"=>
NB<= "0010100010110000101"; -- 600 Bauds
when "0011"=>
NB<= "0001010001011000010"; -- 1200 Bauds
when "0100"=>
NB<= "0000101000101100001"; -- 2400 Bauds
when "0101"=>
NB<= "0000010100010110000"; -- 4800 Bauds
when "0110"=>
NB<= "0000001010001011000"; -- 9600 Bauds
when "0111"=>
NB<= "0000000110110010000"; -- 14400 Bauds
when "1000"=>
NB<= "0000000101000101100"; -- 19200 Bauds
when "1001"=>
NB<= "0000000010100010110"; -- 38400 Bauds
when "1010"=>
NB<= "0000000001101100100"; -- 57600 Bauds
when "1011"=>
NB<= "0000000000110110010"; -- 115200 Bauds
when "1100"=>
NB<= "0000000000110000110"; -- 128000 Bauds
when "1101"=>
NB<= "0000000000011000011"; -- 256000 Bauds
when others=>
NB<= "0000000000000000000"; -- 0 Bauds
end case;
if(Qp= "0000000000000000000")then
Qn<= NB;
FBaud<= '1';
else
Qn<= Qp-1;
FBaud<= '0';
end if;
end process COMB;
FF: process(RST,CLK)
begin
if(RST='0')then
Qp <= (others=>'0');
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process FF;
end simple;
\end{minted}
\section{FsmWrite}
\begin{minted}[breaklines,linenos=true,numberblanklines=true]{vhdl}
library IEEE;
use IEEE.std_logic_1164.all;
entity FsmWrite is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud: in std_logic;
EOT : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end FsmWrite;
architecture simple of FsmWrite is
signal Qp, Qn : std_logic_vector(3 downto 0);
begin
COMB: process(Qp,STR,FBaud)
begin
case Qp is
when "0000" =>
CTRL<= "0000";-- Hold
EOT<= '1';
if(STR= '0')then
Qn<= Qp;
else
Qn<= "0001";
end if;
when "0001" =>
CTRL<= "0000";-- Hold
EOT<= '0';
if(FBaud= '1')then
Qn<= "0010";
else
Qn<= Qp;
end if;
when "0010" =>
CTRL<= "0001"; -- Start
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0011";
end if;
when "0011" =>
CTRL<= "0010"; -- Bit 0
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0100";
end if;
when "0100" =>
CTRL<= "0011"; -- Bit 1
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0101";
end if;
when "0101" =>
CTRL<= "0100"; -- Bit2
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0110";
end if;
when "0110" =>
CTRL<= "0101"; -- Bit 3
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0111";
end if;
when "0111" =>
CTRL<= "0110"; -- Bit 4
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1000";
end if;
when "1000" =>
CTRL<= "0111"; -- Bit 5
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1001";
end if;
when "1001" =>
CTRL<= "1000"; -- Bit 6
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1010";
end if;
when "1010" =>
CTRL<= "1001"; -- Bit 7
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1011";
end if;
when "1011" =>
CTRL<= "1010"; -- Stop
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1100";
end if;
when "1100" =>
CTRL<= "1010";
EOT<= '0';
IF (STR='1') THEN
Qn <=Qp;
ELSE
Qn<="1101";
END IF;
when others =>
CTRL<= "0000";
EOT<= '1';
Qn<= "0000";
end case;
end process COMB;
FF: process(RST,CLK)
begin
if(RST='0')then
Qp<= "0000";
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process;
end simple;
\end{minted}
\end{document}
我已经尝试使用figure*，但问题是它使其成为一张完整的图片，所以我无法看到整个代码。
请帮忙！！！
答案1
\onecolumn之后立即使用\appendices；如果需要，您可以切换回来使用\twocolumn（每个命令都会开始一个新页面）：
\documentclass{IEEEtran}
\usepackage{lipsum}
\usepackage[]{minted}
\begin{document}
\section{Introduction}
\lipsum
\section{Material}
\lipsum
\appendices
\section{BaudRate}
\begin{minted}[breaklines,linenos=true,numberblanklines=true]{vhdl}
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRate is
port(
RST :in std_logic;
CLK :in std_logic;
NBaud :in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud :out std_logic -- Base frecuency
);
end BaudRate;
architecture simple of BaudRate is
signal Qp,Qn,NB : std_logic_vector(18 downto 0);
begin
COMB: process(NBaud,Qp)
begin
case NBaud is
when "0000"=>
NB<= "1101110111110010001"; -- 110 Bauds
when "0001"=>
NB<= "0101000101100001010"; -- 300 Bauds
when "0010"=>
NB<= "0010100010110000101"; -- 600 Bauds
when "0011"=>
NB<= "0001010001011000010"; -- 1200 Bauds
when "0100"=>
NB<= "0000101000101100001"; -- 2400 Bauds
when "0101"=>
NB<= "0000010100010110000"; -- 4800 Bauds
when "0110"=>
NB<= "0000001010001011000"; -- 9600 Bauds
when "0111"=>
NB<= "0000000110110010000"; -- 14400 Bauds
when "1000"=>
NB<= "0000000101000101100"; -- 19200 Bauds
when "1001"=>
NB<= "0000000010100010110"; -- 38400 Bauds
when "1010"=>
NB<= "0000000001101100100"; -- 57600 Bauds
when "1011"=>
NB<= "0000000000110110010"; -- 115200 Bauds
when "1100"=>
NB<= "0000000000110000110"; -- 128000 Bauds
when "1101"=>
NB<= "0000000000011000011"; -- 256000 Bauds
when others=>
NB<= "0000000000000000000"; -- 0 Bauds
end case;
if(Qp= "0000000000000000000")then
Qn<= NB;
FBaud<= '1';
else
Qn<= Qp-1;
FBaud<= '0';
end if;
end process COMB;
FF: process(RST,CLK)
begin
if(RST='0')then
Qp <= (others=>'0');
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process FF;
end simple;
\end{minted}
\section{FsmWrite}
\begin{minted}[breaklines,linenos=true,numberblanklines=true]{vhdl}
library IEEE;
use IEEE.std_logic_1164.all;
entity FsmWrite is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud: in std_logic;
EOT : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end FsmWrite;
architecture simple of FsmWrite is
signal Qp, Qn : std_logic_vector(3 downto 0);
begin
COMB: process(Qp,STR,FBaud)
begin
case Qp is
when "0000" =>
CTRL<= "0000";-- Hold
EOT<= '1';
if(STR= '0')then
Qn<= Qp;
else
Qn<= "0001";
end if;
when "0001" =>
CTRL<= "0000";-- Hold
EOT<= '0';
if(FBaud= '1')then
Qn<= "0010";
else
Qn<= Qp;
end if;
when "0010" =>
CTRL<= "0001"; -- Start
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0011";
end if;
when "0011" =>
CTRL<= "0010"; -- Bit 0
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0100";
end if;
when "0100" =>
CTRL<= "0011"; -- Bit 1
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0101";
end if;
when "0101" =>
CTRL<= "0100"; -- Bit2
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0110";
end if;
when "0110" =>
CTRL<= "0101"; -- Bit 3
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0111";
end if;
when "0111" =>
CTRL<= "0110"; -- Bit 4
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1000";
end if;
when "1000" =>
CTRL<= "0111"; -- Bit 5
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1001";
end if;
when "1001" =>
CTRL<= "1000"; -- Bit 6
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1010";
end if;
when "1010" =>
CTRL<= "1001"; -- Bit 7
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1011";
end if;
when "1011" =>
CTRL<= "1010"; -- Stop
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1100";
end if;
when "1100" =>
CTRL<= "1010";
EOT<= '0';
IF (STR='1') THEN
Qn <=Qp;
ELSE
Qn<="1101";
END IF;
when others =>
CTRL<= "0000";
EOT<= '1';
Qn<= "0000";
end case;
end process COMB;
FF: process(RST,CLK)
begin
if(RST='0')then
Qp<= "0000";
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process;
end simple;
\end{minted}
\end{document}
