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\confheader{ 2020 IEEE International Conference on Computation, Automation and Knowledge Management (ICCAKM)
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\begin{document}
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\title{Performance Analysis of Physically
Unclonable Function Based on Voltage Divider Arrays}
\author{\IEEEauthorblockN{Sumit Chaudhary$^{1}$}
\IEEEauthorblockA{\textit{Dept. of Electronics and Communication} \\
\textit{MNIT Jaipur, India}\\
[email protected]}
\and
\IEEEauthorblockN{Chitrakant Sahu$^{2}$}
\IEEEauthorblockA{\textit{Dept. of Electronics and Communication} \\
\textit{MNIT Jaipur, India}\\
[email protected]}}
\maketitle
\begin{abstract}
A Physical Unclonable Function (PUF) is a chip-specific random function in which security primitives rely on the inherent randomness of integrated circuit fabrication. It can be used for chip authentication or identification and generation of the key. The most of the PUFs uses the delay to generate
set of responses, however, because of linear separability of the
response function it results in delay along circuit paths, hence, they are vulnerable to various kind of attacks. In this paper, a new physical Unclonable function is proposed that uses the concept of mismatch between MOSFETs
arranged in a voltage divider configuration. All the transistors
are subjected to stochastic variability, and they are operated in
the subthreshold region. The random binary output is generated
\end{abstract}
\section{Introduction}
In today's era of information secuirity, cryptographic key generation and secure validation of devices are the pervasive need\cite{1,2}. For that physically unclonable function (PUFs) speak to a rising and promising innovation\cite{3}.
A PUF is an entity which is chip-specific, and generate a chip-specific output that usually is a binary number and unique for every chip\cite{8}. PUFs derive their randomness from the production variability of the IC manufacturing process which is undesirable and uncontrolled to generate the chip-specific output. This output can be seen as the biometric(fingerprint) of a chip. Instead of storing secret keys in a digital memory as in conventional security solutions, PUFs get the keys from the physical qualities of coordinated circuits. Since the produced die-specific keys depend impressively upon a many physical quantities that the assembling procedure can't control and that can't be remotely estimated, the protected gadget confirmation is guaranteed\cite{4}.
Silicon-based physical unclonable functions are changeability mindful circuits that execute die-specific challenge-response systems by using fabricating process variations\cite{5,6}. As an outcome, random bit generates through the intrinsic variability in circuit elements. Generally, silicon-PUF plans utilize memory-based or delay-based\cite{7} approaches to get a random response in the PUF. Recently, more robust silicon based Physical unclonable function topologies have been proposed, which are based on mono-stable and static analog circuits that use mismatch between outputs of voltage generators and current mirror branches\cite{Kalyanaraman}.
In this work, a static physical unclonable function using voltage dividers array (VDA) on 45-nm technology MOSFET is proposed. The two-transistor voltage divider uses the subthreshold operation of MOSFET to spotlight the random process fluctuations. The proposed array on account of its high fluctuation, the proposed PUF arrangement shows high robustness against supply voltage, noise \& temperature variations.
%\section{What Is a Physical Unclonable Function?}
%{\bf {\large Physical}} means a physical entity, in distinction to an algorithmic rule or an identical function. If physically is employed,the meaning changes since now it becomes an adverb to unclonable which means the function is clonable in general but can not be clonable in physical way.\\
%{\bf {\large Unclonable}} implies that a thing cannot be replicated. For PUFs this can be true in practice. In theory, PUFs are clonable.\\
%\begin{figure}[h!]
% \centering
% \includegraphics[width=2.0in]{fig1.jpg}
% \caption{PUFs The fingerprint of devices\cite{8}}
%
%\end{figure}
%{\bf {\large Function}} According to mathematical concepts, a Physical unclonable function is not even strictly a function, regarding mathematics, that an input value is linked with one specific output value. Since the output of a PUF is usually noisy, it happens that an input
%produces different outputs. So typically PUF is not a mathematical function..
%
%
%
%\section{Challenge and Response}
%An input to a PUF is referred to as the challenge, and the generated output is referred to as the response as shown in the figure-1.2. An applied challenge and its response are usually referred to as the challenge-response pair or a CRP. These terms are from the field of security, where challenge-response authentication is a method that checks an identity by requiring right validation data in response to a challenge.
%
%\begin{figure}
% \centering
% \includegraphics[width=10cm]{fig1.jpg}
% \caption{ On-chip Physical Unclonable Function (PUF)}
% \end{figure}
%
%
%
%\section{Silicon PUFs and Non-Silicon PUFs}
%In this work, we concentrate just on the silicon-based PUF plans which are outlined and created much the same as some other CMOS circuit, permitting easy integration with existing silicon-based security system designs. Note that other non-silicon based PUF usage have been proposed in writing, e.g., optical PUFs\cite{Pappu2026}, however troubles in incorporation with standard CMOS plan and producing stream constrain their practicality.
%\section{Intrinsic and Non-intrinsic PUFs}
%An classification of Physical unclonable function based on their development characteristics is that of intrinsic PUFs and extrinsic PUFs. Intrinsic PUFs first proposed by Guajardo et al\cite{Guajardo}. In a somewhat adjusted form, we consider that a PUF construction needs to have at least two conditions to be known an intrinsic PUF: (i) its evaluations are performed internally by embedded measurement instrumentation, and (ii) its random instance-specific features are implicitly introduced at the time of its production process. SRAM PUF, Butterfly PUF, Bistable Ring PUF are some examples of intrinsic PUFs.
%\paragraph*{}A assortment of Physical unclonable function implementaions have been proposed which we mark as non-intrinsic according to this categorization,e.g. :
%\par The optical PUF is non-intrinsic because it is evaluated externally (by investigating the specked pattern) \& its random characteristic are explicitly introduced (by solving the scattering particles). The coating PUF is likewise non-intrinsic: despite the fact that it can be internally evaluated on a si chip. But its randomness is generated during production explicitly (by solving the dielectric particles).
%\section{The PUF Core}
%At the center of a si PUF, is a circuit (the PUF core) that produces irregular bits. The PUF core circuit leverages the generally tiny and uncontrolled irregular producing process variations to generate chip-specific, unique, random arrangement of bits. A PUF gets all its randomness from these basic PUF core bits, and henceforth great PUF core bits is basic in accomplishing a PUF of top quality. Figure 1.3 shows
%\begin{figure}[h!]
% \centering
% \includegraphics[width= 10cm]{fig3.jpg}
% \caption{ A typical PUF system generates a response when provided with a challenge. The PUF core is the source of entropy for the PUF system. The challenge and response may be conditioned using scramblers. Error correction may be implemented to increase the reliability of the generated response.}
%
%\end{figure}
%
%
%
%
%
%how a PUF core circuit might be inserted in a PUF system for the generation of the response when provided with an input challenge. As shown in Figure 1.3, peripheral circuits may implement input or output scramblers to condition the challenge and response for added security. Error correction may be implemented to correct
%errors in the raw response from the PUF core. The response of a PUF should have the following security properties:
%
%\begin{itemize}
% \item Unique: chip-specific, similar to a silicon fingerprint.
% \item Random: impossible or difficult to model the response.
% \item Reliable: Invariable across environmental variations and aging.
%\end{itemize}
%
%\paragraph*{} In this thesis, as in most of the literature, the term “PUF” is often used to describe the “PUF core” that generates a single response bit.
%
%
\section{Introduction}
In today's era of information secuirity, cryptographic key generation and secure validation of devices are the pervasive need\cite{1,2}. For that physically unclonable function (PUFs) speak to a rising and promising innovation\cite{3}.
A PUF is an entity which is chip-specific, and generate a chip-specific output that usually is a binary number and unique for every chip\cite{8}. PUFs derive their randomness from the production variability of the IC manufacturing process which is undesirable and uncontrolled to generate the chip-specific output. This output can be seen as the biometric(fingerprint) of a chip. Instead of storing secret keys in a digital memory as in conventional security solutions, PUFs get the keys from the physical qualities of coordinated circuits. Since the produced die-specific keys depend impressively upon a many physical quantities that the assembling procedure can't control and that can't be remotely estimated, the protected gadget confirmation is guaranteed\cite{4}.
Silicon-based physical unclonable functions are changeability mindful circuits that execute die-specific challenge-response systems by using fabricating process variations\cite{5,6}. As an outcome, random bit generates through the intrinsic variability in circuit elements. Generally, silicon-PUF plans utilize memory-based or delay-based\cite{7} approaches to get a random response in the PUF. Recently, more robust silicon based Physical unclonable function topologies have been proposed, which are based on mono-stable and static analog circuits that use mismatch between outputs of voltage generators and current mirror branches\cite{Kalyanaraman}.
In this work, a static physical unclonable function using voltage dividers array (VDA) on 45-nm technology MOSFET is proposed. The two-transistor voltage divider uses the subthreshold operation of MOSFET to spotlight the random process fluctuations. The proposed array on account of its high fluctuation, the proposed PUF arrangement shows high robustness against supply voltage, noise \& temperature variations.
%\section{What Is a Physical Unclonable Function?}
%{\bf {\large Physical}} means a physical entity, in distinction to an algorithmic rule or an identical function. If physically is employed,the meaning changes since now it becomes an adverb to unclonable which means the function is clonable in general but can not be clonable in physical way.\\
%{\bf {\large Unclonable}} implies that a thing cannot be replicated. For PUFs this can be true in practice. In theory, PUFs are clonable.\\
%\begin{figure}[h!]
% \centering
% \includegraphics[width=2.0in]{fig1.jpg}
% \caption{PUFs The fingerprint of devices\cite{8}}
%
%\end{figure}
%{\bf {\large Function}} According to mathematical concepts, a Physical unclonable function is not even strictly a function, regarding mathematics, that an input value is linked with one specific output value. Since the output of a PUF is usually noisy, it happens that an input
%produces different outputs. So typically PUF is not a mathematical function..
%
%
%
%\section{Challenge and Response}
%An input to a PUF is referred to as the challenge, and the generated output is referred to as the response as shown in the figure-1.2. An applied challenge and its response are usually referred to as the challenge-response pair or a CRP. These terms are from the field of security, where challenge-response authentication is a method that checks an identity by requiring right validation data in response to a challenge.
%
%\begin{figure}
% \centering
% \includegraphics[width=10cm]{fig1.jpg}
% \caption{ On-chip Physical Unclonable Function (PUF)}
% \end{figure}
%
%
%
%\section{Silicon PUFs and Non-Silicon PUFs}
%In this work, we concentrate just on the silicon-based PUF plans which are outlined and created much the same as some other CMOS circuit, permitting easy integration with existing silicon-based security system designs. Note that other non-silicon based PUF usage have been proposed in writing, e.g., optical PUFs\cite{Pappu2026}, however troubles in incorporation with standard CMOS plan and producing stream constrain their practicality.
%\section{Intrinsic and Non-intrinsic PUFs}
%An classification of Physical unclonable function based on their development characteristics is that of intrinsic PUFs and extrinsic PUFs. Intrinsic PUFs first proposed by Guajardo et al\cite{Guajardo}. In a somewhat adjusted form, we consider that a PUF construction needs to have at least two conditions to be known an intrinsic PUF: (i) its evaluations are performed internally by embedded measurement instrumentation, and (ii) its random instance-specific features are implicitly introduced at the time of its production process. SRAM PUF, Butterfly PUF, Bistable Ring PUF are some examples of intrinsic PUFs.
%\paragraph*{}A assortment of Physical unclonable function implementaions have been proposed which we mark as non-intrinsic according to this categorization,e.g. :
%\par The optical PUF is non-intrinsic because it is evaluated externally (by investigating the specked pattern) \& its random characteristic are explicitly introduced (by solving the scattering particles). The coating PUF is likewise non-intrinsic: despite the fact that it can be internally evaluated on a si chip. But its randomness is generated during production explicitly (by solving the dielectric particles).
%\section{The PUF Core}
%At the center of a si PUF, is a circuit (the PUF core) that produces irregular bits. The PUF core circuit leverages the generally tiny and uncontrolled irregular producing process variations to generate chip-specific, unique, random arrangement of bits. A PUF gets all its randomness from these basic PUF core bits, and henceforth great PUF core bits is basic in accomplishing a PUF of top quality. Figure 1.3 shows
%\begin{figure}[h!]
% \centering
% \includegraphics[width= 10cm]{fig3.jpg}
% \caption{ A typical PUF system generates a response when provided with a challenge. The PUF core is the source of entropy for the PUF system. The challenge and response may be conditioned using scramblers. Error correction may be implemented to increase the reliability of the generated response.}
%
%\end{figure}
%
%
%
%
%
%how a PUF core circuit might be inserted in a PUF system for the generation of the response when provided with an input challenge. As shown in Figure 1.3, peripheral circuits may implement input or output scramblers to condition the challenge and response for added security. Error correction may be implemented to correct
%errors in the raw response from the PUF core. The response of a PUF should have the following security properties:
%
%\begin{itemize}
% \item Unique: chip-specific, similar to a silicon fingerprint.
% \item Random: impossible or difficult to model the response.
% \item Reliable: Invariable across environmental variations and aging.
%\end{itemize}
%
%\paragraph*{} In this thesis, as in most of the literature, the term “PUF” is often used to describe the “PUF core” that generates a single response bit.
%
%
\end{document}