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在表格旁边绘制 Circuitikz 图会产生 hbox 警告

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在表格旁边绘制 Circuitikz 图会产生 hbox 警告

我正在尝试使用 minipages 在表格旁边绘制 Circuitikz 图，但包含该图的 minipage 出现过满的水平框警告，因此该图与表格重叠。有什么办法可以解决这个问题吗？以下是我写的内容以及示例：

\begin{minipage}[b]{0.5\linewidth}
  \centering
  \begin{circuitikz}
    
    % AND logic gates
    \node[ieeestd and port] (and1) at (0,2) {};
    \node[ieeestd and port] (and2) at (0,-2) {};

    % NOR logic gates
    \draw (and1.out) -- ++(2.5,0) node[ieeestd nor port,anchor=in 1] (nor1) {};
    \draw (and2.out) -- ++(2.5,0) node[ieeestd nor port,anchor=in 2] (nor2) {};

    \draw (nor1.in 2) -| ++ (-0.2,-0.85) -- ++(3,-1.5) coordinate(a) |- (nor2.out);
    \draw (nor2.in 1) -| ++ (-0.2,0.85) -- ++(3,1.5) |- (nor1.out);

    % Labels
    \draw (and1.in 2) -- ++(-0.75,0) node[left]{J};
    \draw (and2.in 1) -- ++(-0.75,0) node[left]{K};

    \draw (nor1.out -| a) -- ++(0.75,0) node[right]{$\mathrm{\bar Q}$};
    \draw (nor2.out -| a) -- ++(0.75,0) node[right]{$\mathrm{Q}$};

    % Additional
    \draw (and1.in 1) -- ++(0,.5)
        to (6.7,2.8) to (6.7,1.715)
    ;
    \draw (and2.in 2) -- ++(0,-.5)
        to (6.7,-2.8) to (6.7,-1.715)
    ;


  \end{circuitikz}
\end{minipage}\hfill
\begin{minipage}[b]{0.5\linewidth}
    \centering
    {\bfseries\strut JK latch truth table}
    \begin{tabular}{|l|l|l|l|}
      \hline
      {\boldmath $\mathrm{J}$} & {\boldmath $\mathrm{K}$} & {\boldmath $\mathrm{Q_{state}}$} & \textbf{Change} \\ \hline
      0            & 0            & $Q$                  & No change       \\ \hline
      0            & 1            & 0                    & Reset           \\ \hline
      1            & 0            & 1                    & Set             \\ \hline
      1            & 1            & $\bar Q$             & Toggle          \\ \hline
    \end{tabular}
\end{minipage}

答案1

如果要在图中保持相同的比例，并填充线条，则需要进行以下更改：

  1. 两个小页面0.5\linewidth正好填满了这一行，所以你需要以一个开始\noindent（至少在标准类中article；你没有提供一个全 MWE所以我们不知道你正在使用哪个类）；

  2. 要将所有内容对齐到底部，正如你试图做的那样，你需要对齐还底部的表格；

  3. 你可以减少电路中的长引线@js 比布拉建议，或者你可以用 --- 缩小电路，scale=..., transform shape这也会缩小字符字体；如果不想这样，你可以对逻辑端口使用“类”比例因子（见circutitz手动的）。

在此处输入图片描述

\documentclass{article}
\usepackage[T1]{fontenc}
\usepackage[utf8]{inputenc}
\usepackage[RPvoltages]{circuitikz}
\overfullrule=5pt
\begin{document}
  \noindent
  \begin{minipage}[b]{0.5\linewidth}
  \centering
  \begin{circuitikz}[scale=0.5, transform shape]
    
    % AND logic gates
    \node[ieeestd and port] (and1) at (0,2) {};
    \node[ieeestd and port] (and2) at (0,-2) {};
    % NOR logic gates
    \draw (and1.out) -- ++(2.5,0) node[ieeestd nor port,anchor=in 1] (nor1) {};
    \draw (and2.out) -- ++(2.5,0) node[ieeestd nor port,anchor=in 2] (nor2) {};
    \draw (nor1.in 2) -| ++ (-0.2,-0.85) -- ++(3,-1.5) coordinate(a) |- (nor2.out);
    \draw (nor2.in 1) -| ++ (-0.2,0.85) -- ++(3,1.5) |- (nor1.out);
    % Labels
    \draw (and1.in 2) -- ++(-0.75,0) node[left]{J};
    \draw (and2.in 1) -- ++(-0.75,0) node[left]{K};
    \draw (nor1.out -| a) -- ++(0.75,0) node[right]{$\mathrm{\bar Q}$};
    \draw (nor2.out -| a) -- ++(0.75,0) node[right]{$\mathrm{Q}$};
    % Additional
    \draw (and1.in 1) -- ++(0,.5)
        to (6.7,2.8) to (6.7,1.715)
    ;
    \draw (and2.in 2) -- ++(0,-.5)
        to (6.7,-2.8) to (6.7,-1.715)
    ;
  \end{circuitikz}
\end{minipage}\hfill
\begin{minipage}[b]{0.5\linewidth}
    \centering
    {\bfseries\strut JK latch truth table}
    \begin{tabular}[b]{|l|l|l|l|}
      \hline
      {\boldmath $\mathrm{J}$} & {\boldmath $\mathrm{K}$} & {\boldmath $\mathrm{Q_{state}}$} & \textbf{Change} \\ \hline
      0            & 0            & $Q$                  & No change       \\ \hline
      0            & 1            & 0                    & Reset           \\ \hline
      1            & 0            & 1                    & Set             \\ \hline
      1            & 1            & $\bar Q$             & Toggle          \\ \hline
    \end{tabular}
\end{minipage}
\end{document}

答案2

在此处输入图片描述

\documentclass[10pt,a4paper]{article}

\usepackage[left=2.00cm, right=1.00cm]{geometry}
\usepackage{circuitikz,booktabs}
\begin{document}
    {\centering
    \begin{minipage}[b]{0.4\textwidth}
        \begin{circuitikz}
            % AND logic gates
            \node[ieeestd and port] (and1) at (0,2) {};
            \node[ieeestd and port] (and2) at (0,-2) {};
            % NOR logic gates
            \draw (and1.out) -- ++(1,0) node[ieeestd nor port,anchor=in 1] (nor1) {};
            \draw (and2.out) -- ++(1,0) node[ieeestd nor port,anchor=in 2] (nor2) {};
            \draw (nor1.in 2) |- ++ (0,-0.85) -- ++(2,-1.5)|-coordinate(b) (nor2.out);
            \draw (nor2.in 1) |- ++ (0,0.85) -- ++(2,1.5) |- coordinate(a)(nor1.out);
            % Labels
            \draw (and1.in 2)  node[left]{J};
            \draw (and2.in 1) node[left]{K};
            \draw (nor1.out)  node[right]{$\mathrm{\bar Q}$};
            \draw (nor2.out) node[right]{$\mathrm{Q}$};
            % Additional
            \draw (and1.in 1)++(0.2,0) -- ++(0,.5)-|(a);
            \draw (and2.in 2)++(0.2,0) -- ++(0,-.5)-|(b);
            \end{circuitikz}
    \end{minipage}
    \begin{minipage}[b]{0.45\textwidth}
        \begin{tabular}{llll}
            \toprule
            \multicolumn{4}{c}{\bfseries\strut JK latch truth table}\\\midrule
            {\boldmath $\mathrm{J}$} & {\boldmath $\mathrm{K}$} & {\boldmath $\mathrm{Q_{state}}$} & \textbf{Change} \\ \midrule
            0            & 0            & $Q$                  & No change       \\ \midrule
            0            & 1            & 0                    & Reset           \\ \midrule
            1            & 0            & 1                    & Set             \\ \midrule
            1            & 1            & $\bar Q$             & Toggle          \\ \bottomrule
        \end{tabular}
     \par\vspace{0pt}
    \end{minipage}}
\end{document}

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